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Dominik Šišejković Webinar

Hardware Trojans vs. Logic Locking: Challenges and Opportunities

By Dominik Šišejković

Chief Engineer & PhD candidate at RWTH Aachen University

Date & Time: 22nd of June 2021, 5:00 PM CEST

Talk Title:

Hardware Trojans vs. Logic Locking: Challenges and Opportunities


As the designated root of trust, hardware is undoubtedly the most critical layer to security in modern electronic systems. However, due to the involvement of third parties in the integrated circuit design and fabrication flow, protecting the hardware against malicious modification, i.e., hardware Trojans, has become ever more complex. This challenge has triggered great interest in the academic and industrial sector to explore novel hardware design for trust methodologies. In particular, logic locking—a hardware obfuscation technique—has evolved as a prominent method to safeguard hardware designs throughout the integrated circuit supply chain.

In this talk, we take a holistic view on logic locking schemes. First, we analyse the role of this technology in protecting against hardware Trojans. Second, we take a closer look at the landscape of attack vectors that can compromise the security of logic locking. We further introduce an extensible framework for the application of logic locking policies to complex hardware designs and demonstrate its application for the development of the first logic-locked processor. Furthermore, we discuss the challenges and opportunities of logic locking in the era of machine learning. Finally, we take a look at logic locking in a beyond-CMOS setting.

Speaker Bio:

Dominik Šišejković received the B.Sc. and M.Sc. degree in computing (software engineering and information systems) from the Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia, in 2014 and 2016 respectively. In September 2016, he started working as a Ph.D. student and research assistant at the Institute for Communication Technologies and Embedded Systems. Since September 2017, he is working as the Technical Project Officer of the EU-funded project TETRAMAX; facilitating technology transfer from academia to European SMEs. From October 2018, he is the Chief Engineer of the Chair for Software for Systems on Silicon. In addition, he was directly involved in the design and implementation of the logic locking framework that was applied for the production of the first logic locked RISC-V processor core on the market. Since 2019, he co-organizes the annual SeHAS workshop on secure hardware, architectures and operating systems at the HiPEAC conference. Since 2020, he is part of the technical committee for the hardware and systems security track at the International Symposium on Quality Electronic Design (ISQED). He received the ICT Young Researcher Award 2020 by RWTH Aachen University for significant contributions in the ICT research area. Moreover, he was awarded the HiPEAC Technology Transfer Award 2020 for successfully transferring a scalable logic locking framework for hardware integrity protection to industry. Since 2020, he is an ACM professional member.