Workshop Title:

How to Build & Secure a RISC-V Embedded System

Abstract:

The impressive growth of the RISC-V ecosystem is on everyone’s lips. Originally developed at UC Berkeley, the free and open ISA promises to bring the innovation and collaboration of the open source community to the hardware world - and to dramatically disrupt the whole semiconductor industry in the process. However, hardware and software engineers used to traditional closed-source proprietary architectures and tools may find difficult to orient themselves in this highly-fragmented galaxy of RISC-V technologies, open source tools and development frameworks.

So really the question is: How do I get started with RISC-V?
This class will show exactly that: how to download, build, configure, debug and test a completely free and open source RISC-V development environment.

Part 1

• download and burn to FPGA a fully customizable RISC-V softcore (33-bit Rocket)
• download and build the full RISC-V GNU toolchain - both 32-bit and 64-bits
• download and build the full OpenOCD / JTAG debug stack
• download and configure Eclipse IDE with the RISC-V embedded development plugin
• develop, compile, debug and test on actual hardware your first RISC-V “Hello World” application

Part 2

• develop a secure embedded application with front-end, Root of Trust and Secure Boot functions
• install and configure a multi-domain Trusted Execution Environment
• “plug-in” the functions to the Trusted Execution Environment
• flash the resulting firmware to an actual FPGA board running a RISC-V Rocket core
• run the complete application and demonstration the overall safety and security of the system

This class is a must-attend for SoC designers, system architects, and software developers who want to properly implement secure RISC-V systems but don’t want to take the time and the risk of figuring out the necessary moving parts themselves.

Speaker Bio:

Cesare Garlati is an internationally renowned expert in information security. Former Vice President of mobile security at Trend Micro, Cesare currently serves as Chief Security Strategist at prpl Foundation – a technology nonprofit dedicated to enabling security and interoperability of embedded systems. Cesare is a long-time supporter of the RISC-V Foundation, a key member of the RISC-V security group and founder of Hex Five Security – the creator of the first trusted execution environment for RISC-V.
Cesare has been frequently quoted in the press, including such media outlets as The Economist, Financial Times, The Register, The Guardian, ZD Net, SC Magazine, Computing and CBS News. An accomplished public speaker, Cesare also has delivered presentations and highlighted speeches at many tier-1 events, including Embedded World Conference, IoT World, Mobile World Congress, Gartner Security Summits, IDC CIO Forums, CTIA Applications, CSA Congress, DAC, IoT Innovation and many editions of the RSA Conference – the world’s leading information security event.
Cesare holds a U.C. Berkeley MBA, a Master in Electrical Engineering and Computer Sciences, professional certifications from Microsoft, Cisco and Oracle, and he is a Fellow of the Cloud Security Alliance, where he founded and chaired the Mobile Security and IoT Security groups.

Dr. Sandro Pinto is a Research Scientist and Invited Professor at the University of Minho, Portugal. He holds a Ph.D. in Electronics and Computer Engineering. During his Ph.D., Sandro was a visiting researcher at the Asian Institute of Technology (Thailand), University of Wurzburg (Germany), and Jilin University (China). Sandro has a deep academic background and several years of industry collaboration focusing on operating systems, virtualization, and security for embedded, cyber-physical, and IoT-based systems. He has published several scientific papers in top-tier conferences/journals and is a skilled presenter with speaking experience in several academic and industrial conferences. Sandro is a long-term supporter of open source projects, a proud member of the RISC-V Foundation, and is currently helping Hex-Five to make RISC-V security practical at scale.